1. Field of the Invention
The present invention relates to a data separation operation performed by a floppy disk controller and, more particularly, to a data separation circuit and method which use a digital phase locked loop (DPLL).
2. Discussion of Related Art
With reference to the attached drawings, a conventional data separation circuit will be described below. FIG. 1 is a block diagram of a conventional data separation circuit. A conventional internal data separation circuit roughly includes an analog PLL part and its related circuits. As shown in FIG. 1, the circuit has a prescaler 1 for leveling the magnitude of the signal output from a reference crystal XTAL, which has a predetermined reference frequency of 24 MHz, into a specific size; a reference clock generating part 2 for receiving the frequency levelled by the prescaler 1 and generating a system reference clock; a first frequency divider 3 for dividing the frequency levelled by the prescaler 1; a 1/4 cycle delaying part 4 for delaying by 1/4 cycle of the system reference clock the data read out of the disk driver in synchronization with the reference clock of the reference clock generating part 2; and a MUX 5 for multiplexing the frequency-divided signal output by the first frequency divider 3 and the delayed read data signal output by the 1/4 cycle delaying part 4 based on a signal indicative of a read gate's logic state. The read gate becomes logic high when the read data is applied (See FIGS. 4C and 4D).
A zero-phase error detecting part 6 also receives the signal indicative of the read gate's logic state and the delayed read data signal, and detects the zero phase error. An enable logic part 7 outputs an enable signal in accordance with the read data and the read gate's logic state to an analog phase locked loop circuit (PLL) 14.
As shown in FIG. 1, the analog PLL 14 includes a phase comparing part 8 for comparing, in accordance with the enable signal, the output signal from the MUX 5 with the frequency-divided signal fed-back by the analog PLL 14 to thereby detect the phase difference between these signals and generate an up/down signal. The analog PLL 14 further includes an electric charge pump 9 for outputting a control voltage which varies with the frequency and phase of the clock signal by charging/discharging in response to the up/down signal output by the phase comparing part 8; a loop filter 10 for controlling the width and magnitude of the control voltage, which has a ripple form, produced by the charge/discharge currents of the electric charge pump 9; a voltage controlled oscillator (VCO) 11 for generating, in synchronization with the reference clock, a signal whose frequency varies in accordance with the control voltage; and a second frequency divider 12 for determining a frequency-dividing ratio according to the data rate to thereby frequency-divide the oscillating frequency of the signal output from the VCO 11.
The circuit of FIG. 1 also includes a data/clock signal outputting part 13 for dividing a data and a clock signal from the delayed read data signal output by the 1/4 cycle delaying part 4 based on the frequency-dividing signal output by the second frequency divider 12. The data/clock signal outputting part 13 then outputs the divided clock and data signals.
The thus-structured conventional data separation circuit divides data by controlling the VCO frequency, gain, and current applied to the circuit according to various conditions such as the data rate. While the conventional data separation circuit effectively retrieves data, designing such a circuit is quite difficult. If the data separation circuit design includes an analog PLL, as in the conventional art, the size of the circuit increases. As a result, additional controls, for instance, for VCO frequency, gain, and component current are thus needed for the data separation operation. Consequently, external influences can make the circuit unstable.